As computing systems are advancing, the components therein are becoming more complex. As a result, the interconnect architecture to couple and communicate between the components is also increasing in complexity to ensure bandwidth requirements are met for optimal component operation. Furthermore, different market segments demand different aspects of interconnect architectures to suit the market's needs.
A system-on-a-chip (SoC) includes a fabric interconnect to connect different devices to system memory. SoCs utilize different fabric interconnect topologies. These fabrics are coherent fabrics. One key characteristic of a chosen SoC topology is the connectivity of the memory controller. In some topologies, the memory controller is connected directly to the coherent fabric so that all central processing units (CPUs) and intellectual property cores (IPs) in the system see a coherent and consistent view of memory. In this topology, hardware in the caching agents (e.g., caching agents in the CPUs) and hardware in the coherent fabric actively manage the state of the caches so that all agents in the SoC observe a consistent view of memory.
In other topologies, the memory controller is connected to a non-coherent fabric or directly to an IP, allowing IPs to access memory without traversing the coherent fabric. In this topology, software uses ordering synchronization, memory fencing, and cache flushing operations from an instruction set architecture (Intel Architecture (IA) instruction set architecture) to manage when and how cacheable data becomes visible to all agents in the SoC. In this topology, hardware is also added to the coherent interconnect fabric that responds to the software initiated transactions to ensure that these software initiated ordering events are handled properly.
Thus, these SoC different topologies used specialized coherent fabrics, one for each topology. The cost and design time required to support multiple different types of fabrics is not a small amount.